The growth in computer applications that require heavy data traffic and the increasing availability of high-speed transmission lines and intelligent communication switches create a need for computer systems able to manage a huge amount of data at high rates. For example, high-speed communication networks may require a central processing unit (CPU) to be interrupted at rates of 20,000-100,000 interrupts per second in response to hundreds various events.
In a network controller chip, interrupt request signals to an external CPU may be produced to direct the CPU's attention to various events associated with data transmission and reception.
To prevent processing bottlenecks, the number of interrupt requests should be reduced. Accordingly, it would be desirable to create an interrupt system that batches interrupt events to reduce the total number of interrupt requests sent to the CPU.